Technical Publications

Semiconductor International*, January 2010 – “The Future of Wafer Cleaning Requires Innovation,” Lam Research Corporation

3D Packaging Newsletter*, December 2009 – “Via first, middle, last, or after?” Sally Cole Johnson for Yole Développement

Solid State Technology*, October 2009 – “Optimization of edge die yield through defectivity reduction,” KLA-Tencor Corporation & Lam Research Corporation

Semiconductor International*, April 2009 – “OEE Focuses a Slow Economy,” Ruth DeJule, Semiconductor International

Solid State Technology-WaferNews*, January 2009 – “In 2009, implement strategies to improve equipment productivity,” Lam Research Corporation

Solid State Technology*, November 2008 – “Raising the bar on wafer edge yield—an etch perspective,” Lam Research Corporation

Semiconductor International*, August 2008 – “Bevel Cleans Enhance Yields by Controlling Edge Defects,” Lam Research Corporation

Semiconductor International*, August 2008 – “Increasing Demands Require New Look at Wafer Cleans,” Aaron Hand, Semiconductor International

EuroAsia Semiconductor*, June 2008 – “The Leading Etch,” Lam Research Corporation

Semiconductor International*, March 2008 – “Through-Silicon Vias: Ready for Volume Manufacturing?,” Peter Singer, Semiconductor International

Semiconductor International*, February 2008 – “Double Patterning: An Etch Perspective,” Lam Research Corporation

Semiconductor International*, January 2008 – “32 nm Marked by Litho, Transistor Changes,” Laura Peters, Semiconductor International

Solid State Technology*, December 2007 – “Manufacturing integration considerations of through-silicon via etching,” Lam Research Corporation

* Note: You will be leaving the Lam Research Corporation website.