WAFER PROCESS SOLUTIONS

Leading the Way for Technology Transitions

FinFET Transistor Structure

Transistors – the “brains” of a chip – are tiny switches that control the flow of electricity, and there can literally be billions of these on a single integrated circuit.

Demand for smaller, more powerful electronics is driving the development of new transistor architectures like 3D FinFET designs and the use of specialty materials such as high-k/metal gates. These in turn allow continued shrinking of device feature sizes.

With dimensions for the latest transistors now at the atomic level, they are extremely challenging to manufacture. Failure to achieve the required structure with precision and control can impact device performance.

  Process Technology Products
Etch Conductor Etch Reactive Ion Etch, ALE Kiyo family
Dielectric Etch Reactive Ion Etch, ALE Flex family
Deposition Metal Films CVD, ALD (Tungsten) ALTUS family
Dielectric Films PECVD, ALD VECTOR family
  Gapfill HDP-CVD SPEED family
Hardmask Films PECVD, ALD VECTOR family
Film Treatment UVTP SOLA family
Strip & Clean Photoresist Removal Dry Strip GAMMA family
Wafer Cleaning Wet Clean EOS, DV-Prime
Bevel Cleaning Dry Plasma Clean Coronus family

 

Example of copper interconnect structure

Copper Interconnect Structure

The interconnect makes up the intricate wiring that connects the billions of individual components (transistors, capacitors, etc.) that can be on a chip.

As smaller and smaller devices are packed closer together, more interconnect levels are needed, and connecting everything becomes increasingly challenging. Novel dielectric materials that boost insulating capacity and techniques that minimize resistance of the metal connections are required.

To produce the latest high-performance electronic devices, advanced interconnect structures involve narrow geometries and complex film layers, which require increasingly flexible and precise process capabilities.

  Process Technology Products
Etch Conductor Etch Reactive Ion Etch, ALE Kiyo family
    Versys Metal family
Dielectric Etch Reactive Ion Etch, ALE Flex family
Deposition
Metal Films ECD (Copper) SABRE family
  CVD, ALD (Tungsten) ALTUS family
Dielectric Films PECVD, ALD VECTOR family
  Gapfill HDP-CVD SPEED family
Hardmask Films PECVD, ALD VECTOR family
Film Treatment UVTP SOLA family
Strip & Clean Photoresist Removal Dry Strip GAMMA family
Wafer Cleaning Wet Clean EOS, Da Vinci, DV-Prime
Bevel Cleaning Dry Plasma Clean Coronus family

 

Example of multiple patterning process steps

Multiple Patterning Process Steps

Patterning refers to the set of process steps that use a mask—like a stencil or blueprint—to define the extremely small, intricate features of an integrated circuit.

With each new generation, device dimensions continue to shrink. For advanced structures, these feature sizes can be too small for conventional patterning and lithography to produce. As a result, techniques like double and even quadruple patterning are used to compensate.

Even as these approaches ease lithography limitations, they create new demands for exceptional process precision and very high film quality in order to accurately produce the fine, dense features required.

  Process Technology Products
Etch Conductor Etch Reactive Ion Etch, ALE Kiyo family
Dielectric Etch Reactive Ion Etch, ALE Flex family
Deposition Dielectric Films PECVD, ALD VECTOR family
Hardmask Films PECVD, ALD VECTOR family
Strip & Clean Photoresist Removal Dry Strip GAMMA family
Wafer Cleaning Wet Clean EOS, DV-Prime
Bevel Cleaning Dry Plasma Clean Coronus family

 

3D NAND Memory Structure

Memory cells – the chip components that store electronic data – include short-term volatile (e.g., DRAM) and long-term non-volatile (e.g., flash) storage types.

The use of flash memory continues to grow for mobile consumer devices, where large amounts of data need to be stored in a compact form. One approach to increase device density for more storage capacity is the use of 3D architectures, in particular for NAND flash.

Because these 3D structures involve creating numerous memory levels at the same time, small errors can be magnified greatly, and therefore exceptional precision and process repeatability control are needed.

  Process Technology Products
Etch Conductor Etch Reactive Ion Etch, ALE Kiyo family
Dielectric Etch Reactive Ion Etch, ALE Flex family
Deposition Metal Films ECD (Copper) SABRE family
  CVD, ALD (Tungsten) ALTUS family
Dielectric Films PECVD, ALD VECTOR family
  Gapfill HDP-CVD SPEED family
Strip & Clean Photoresist Removal Dry Strip GAMMA family
Wafer Cleaning Wet Clean EOS, DV-Prime, Da Vinci
Bevel Cleaning Dry Plasma Clean Coronus family

 

Example of through-silicon via structures

Chips Stacked with TSVs

Packaging refers to the process steps that form the protective enclosure around a finished chip and create the external connections for input/output.

Consumer demand for smaller, faster, and more powerful mobile electronics is driving the development of alternate packaging approaches, such as chip-level and wafer-level packaging (WLP). One technique is the use of through-silicon vias (TSVs), which are conductive pillars of metal that connect stacks of chips.

These strategies generate multiple challenges for the processing steps involved, such as managing a range of feature shapes, multiple material types, and strict thermal budgets.

  Process Technology Products
Etch TSV Etch Deep RIE Syndion family
Deposition Metal Films ECD (Copper & Other) SABRE 3D
  CVD, ALD (Tungsten) ALTUS family
Dielectric Films PECVD VECTOR 3D
Strip & Clean
Photoresist Removal Dry Strip GAMMA family
Wafer Cleaning Wet Clean SP Series

 




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