Packaging refers to the process steps that form the protective enclosure around a finished chip and create the external connections for input/output. Consumer demand for smaller, faster, and more powerful mobile electronics is driving the development of alternate packaging approaches. Strategies include wafer-level packaging – where chips are packaged while still on the wafer, then separated – using bumping, redistribution layers, and fan-out packaging approaches. Another technique is the use of through-silicon vias (TSVs), which are conductive pillars of metal that connect stacks of chips. These strategies generate multiple challenges for the processing steps involved, such as managing a range of feature shapes, multiple material types, and strict thermal budgets.