TECHNICAL GLOSSARY

# A B C D E F G H I J K L M N O P Q R S T U V W X Y Z



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µm
see micron


3D IC
an integrated circuit (IC) formed by stacking wafers and/or dies vertically (three-dimensional) and connecting them electrically using through-silicon vias 


3D NAND
a device architecture in which memory cells are arranged vertically (three-dimensional), rather than horizontally (planar) to increase memory bit density


3D TRANSISTOR
a transistor architecture formed vertically (three-dimensional, for example, a FinFET), rather than horizontally (planar)




A

Å
see angstrom



AHM ALD 
see atomic layer deposition

ALE
ANGSTROM (Å)
a unit of length equal to 1 x 10−10 meters 

ANISOTROPIC
in semiconductor manufacturing, a term used to describe a process that is directional (versus isotropic, or uniformly in all directions)

ANNEAL
a process used to change the properties of materials through controlled heating

ANTI-REFLECTIVE LAYER (ARL)
a thin layer of light-absorbing material deposited on top of reflective materials on the wafer to improve photolithography results

AR
ARL

ASHABLE HARDMASK (AHM)
a carbon-based patterning film often used for its ability to provide better selectivity to and protection of underlying layers than conventional photoresist; easily removed by a dry process, such as ashing

ASHING
a type of strip process that removes organic materials, typically photoresist, by using heat and plasma

ASPECT RATIO (AR)
the comparison of the height to the width of a geometric shape (for example, 20:1)

ATOMIC LAYER DEPOSITION (ALD)
a deposition technique that lays down a thin film, typically a few atomic layers at a time; uses cycles of sequential, self-limiting reactions

ATOMIC LAYER ETCHING (ALE)
an etch technique that removes materials, typically a few atomic layers at a time; uses cycles of sequential, self-limiting reactions



B

BACK END
the set of process steps including packaging (external connection) and device testing that complete semiconductor manufacturing; follows front end processes

BACK-END-OF-LINE (BEOL)
the set of steps that form the interconnect structures (wiring); follows front-end-of-line (transistors) and middle-of-line (contacts) processes

BARRIER
a thin layer deposited between two materials to prevent their interaction

BEOL
see back-end-of-line


BEVEL
the rounded or slanted area of the very edge of a wafer 

BEVEL CLEAN
a process that removes unwanted material from the wafer's edge that can otherwise migrate to the active die area and negatively impact device performance or yield; may be a dry process (using plasma) or wet process (using liquid chemicals) 

BIT LINE
the path used to read and write information to memory cells; connects the sources/drains of the cells in a column that makes up a two-dimensional array 



C

CAPACITIVELY COUPLED PLASMA (CCP)
a type of plasma source in which the plasma is formed between two electrodes, typically closely spaced, which are connected to an RF power supply (one may also be connected to ground)


CAPACITOR
a component used to store an electric charge, consisting of one or more pairs of conductors separated by an insulator; used in both logic and memory devices


CCP
see capacitively coupled plasma


CD
see critical dimension


CHANNEL
the conductive path electrons (or holes) follow through a semiconductor; current flow through the channel is controlled by voltage applied across the gate and source terminals


CHEMICAL VAPOR DEPOSITION (CVD)
a process that uses controlled reactions of volatile chemicals to deposit a dielectric or conductive film


CHIP
short for “microchip”; a set of electronic circuits on a small section of a semiconductor wafer; also called a die


CLEANING
see wafer cleaning


CLEANROOM
an enclosed area strictly controlled for airborne contamination, humidity, and temperature to be suitable for manufacturing semiconductor devices


CMOS
see complementary metal oxide semiconductor


COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS)
a common type of semiconductor technology that uses complementary pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions


CONDUCTOR
a material in which electricity flows easily (for example, a metal) that is used to electrically connect components in a semiconductor device


CONFORMAL
a term used to describe uniform coverage of a layer of material over pre-existing topography; thickness of the layer remains the same everywhere on the surface of the feature


CONTACT
the conductive connection between the transistor and the first interconnect layer


COPPER INTERCONNECT
the connections (wiring) of an integrated circuit using copper as the conductive material; offers higher electrical conductivity (faster) than aluminum interconnect


COPPER OVERBURDEN
excess copper deposited on top of the wafer after filling vias and trenches; later removed using chemical-mechanical planarization (CMP)


CRITICAL DIMENSION (CD)
a dimension that must be precisely fabricated to ensure proper device performance and/or yield


CVD
see chemical vapor deposition



D

DAMASCENE
a technique of forming conductive connections (wiring) between circuits by inlaying conductive materials, such as copper, into insulating layers


DEEP SILICON ETCHING
an anisotropic (directional) plasma etch process that creates high aspect ratio (tall and narrow) features in silicon; applications include MEMS devices and TSV structures


DEFECT
any contamination (such as particles or residues) or structural flaw (such as voids); can negatively impact device performance and/or yield


DEFECTIVITY
a measure of the level or degree of defects, including quantity, size, and type; often a comparison against a desired or acceptable level


DEPOSITION
a process that lays down the insulating or conducting materials that make up a semiconductor device


DESCUM
a process that removes a very light organic residue, for example, at the bottom of a trench; typically a plasma process 


DEVICE GENERATION
see technology node


DIE
a term used to describe a single semiconductor chip on a wafer


DIELECTRIC
a non-conductive material used to insulate conductive components in a device


DIRECTED SELF-ASSEMBLY (DSA)
a patterning technology that uses block co-polymers to define patterns


DOUBLE PATTERNING
a multiple patterning technique that increases feature density by a factor of two compared to using a single lithography step; involves either decomposing the mask into two easier-to-print lithography steps or using self-aligned double patterning (SADP) 


DPT
double patterning technology; see double patterning


DRAM
see dynamic random access memory


DSA
see directed self-assembly


DYNAMIC RANDOM ACCESS MEMORY (DRAM)
a type of volatile memory (needs power to retain data) that can be electrically refreshed; with dynamic RAM, each bit of data is stored in a separate capacitor, which needs to be refreshed repetitively



E

ECD
see electrochemical deposition


ECP
electrochemical plating; see electrochemical deposition


EDGE EXCLUSION (EE)
the outermost distance from the wafer's edge, usually indicated in millimeters, where it is generally more difficult to achieve good process results; the lower the edge exclusion, the larger the wafer area where good process results are achieved


EE
see edge exclusion


ELD
see electroless deposition


ELECTROCHEMICAL DEPOSITION (ECD)
a plating technique that deposits a metal layer by passing an electrical current through a chemical solution using the wafer as an electrode; also referred to as electrochemical plating (ECP) or electroplating


ELECTROLESS DEPOSITION (ELD)
a plating technique that deposits a metal layer using a chemical process and relies on the presence of a reducing agent; unlike electrochemical deposition, electroless deposition does not use external electrical power


ELECTROMIGRATION
the movement of atoms or ions in a metal line (interconnect) during high current flow through momentum transfer from electrons to metal atoms; can create voids in the line and eventually prevent current flow or cause device failure


ELECTROPLATING
see electrochemical deposition


ELECTROSTATIC CHUCK (ESC)
a piece of hardware that holds the wafer in place by using a static voltage field, in contrast to vacuum-based or physical clamping


ESC
see electrostatic chuck


ETCH
a process that selectively removes material to create desired features and patterns of a semiconductor device; includes dry (using plasma) and wet (using liquid chemistries) processes 




F

FAB
a facility that manufactures semiconductor products; short for “fabrication”


FEOL
see front-end-of-line


FET
see field effect transistor


FIELD EFFECT TRANSISTOR (FET)
a type of transistor that uses an electric field to control the electrical conductivity of a channel in a semiconductor material


FINFET
a 3D transistor architecture with tall, fin-like structures that enables smaller overall device dimensions and lower power relative to those with planar (side-by-side) transistors of similar feature sizes


FLASH MEMORY
a non-volatile type of memory (does not need power to retain data) that can be electrically erased and rewritten; a common form of flash memory is NAND


FLIP CHIP
a packaging method that creates electrical connections between semiconductor devices by “flipping” the chip face-down to bond to the external circuitry


FOUNDRY
a wafer fabrication facility that manufactures another company's semiconductor products as a service


FOUP
see front-opening unified pod


FRONT END
the set of wafer processing steps that include forming the transistors (front-end-of-line, FEOL), contacts (middle-of-line, MOL), and wiring (back-end-of-line, BEOL); followed by back end processes


FRONT-END-OF-LINE (FEOL)
the set of process steps to form transistors and other circuit elements (such as resistors and capacitors) that are later connected electrically with middle-of-line (contacts) and back-end-of-line (wiring) processes


FRONT-OPENING UNIFIED POD (FOUP)
a specialized wafer carrier used to transport wafers from one processing tool to the next; used to minimize exposure to contamination



G

GAA
see gate-all-around


GAPFILL
a type of deposition process that fills narrow spaces with insulating or conducting material


GATE
one of three terminals of a field effect transistor; current flow between source and drain terminals is controlled by applying or removing voltage to the gate


GATE STACK
the set of insulating and conducting layers that make up the gate of a field effect transistor


GATE-ALL-AROUND (GAA) FET
a type of three-dimensional, multi-gate field effect transistor (FET) designed to have a gate wrapping around all sides of the channel; improves current flow control while enabling continued transistor scaling; also referred to as nanowire FET




H

HAR
see high aspect ratio


HARDMASK
a film that is more resistant to etching than conventional photoresist, thereby better protecting underling layers from alteration; typically used when high-selectivity etching is required


HDP-CVD
see high-density plasma chemical vapor deposition


HIGH ASPECT RATIO (HAR)
refers to very tall and narrow device features, for example, DRAM capacitor cells; the higher the aspect ratio of a feature, the more challenging it is to create; see also aspect ratio


HIGH-DENSITY PLASMA CHEMICAL VAPOR DEPOSITION (HDP-CVD)
a CVD process that employs an inductively coupled plasma (ICP) source to deposit material; the ICP source generates a higher plasma density than typical occurs in PECVD


HIGH-K DIELECTRIC
an insulating material with a high dielectric constant (k) value (for example, hafnium oxide) that is used in a transistor gate stack to lower transistor leakage



I

IC
see integrated circuit


ICP
see inductively coupled plasma


ILD
see interlayer dielectric


IMD
see intermetal dielectric


INDUCTIVELY COUPLED PLASMA (ICP)
a type of plasma source in which plasma is formed when radio frequency (RF) energy is coupled into a gas by an inductive coil through transformer action


INFLECTION
a revolutionary change in process technology; these changes, in turn, drive development of new semiconductor manufacturing capabilities; examples include the change from aluminum to copper interconnects and the introduction of multiple patterning techniques


INTEGRATED CIRCUIT (IC)
a single, complete semiconductor product of electrically connected components (such as transistors and capacitors) fabricated on the same substrate


INTERCONNECT
the intricate wiring that forms electrical connections between components in an integrated circuit


INTERLAYER DIELECTRIC (ILD)
an insulating material that provides electrical isolation between conducting layers


INTERMETAL DIELECTRIC (IMD)
an insulating material that provides electrical isolation between metal lines


ISOTROPIC
in semiconductor manufacturing, a term used to describe a process that is the same in all directions (versus anisotropic, or directional)




K

K VALUE
dielectric constant, the measure of a material’s ability to store an electric charge




L

LED
see light-emitting diode


LELE
see litho/etch/litho/etch


LIGHT-EMITTING DIODE (LED)
a semiconductor device that emits infrared, visible, or ultraviolet light when an electric current flows through it 


LITHO/ETCH/LITHO/ETCH (LELE)
a double patterning process that involves splitting a given pattern into two less dense patterns to compensate for lithography resolution limitations; each pattern requires one lithography step and one etch step


LITHOGRAPHY
a process that transfers patterns from a photomask to the wafer


LOGIC
a chip consisting of circuit elements that together perform a function using various types of mathematical operations, for example, microprocessors; can be thought of as the “brains” of an electronic device


LOW-K DIELECTRIC
an insulating material that has a dielectric constant (k value) lower than that of silicon dioxide (~3.9); commonly used in interconnect structures




M

MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM)
a non-volatile memory technology that uses magnetic storage elements rather than conventional electric charges to store data


MASK
a layer of material that protects certain areas of the wafer while other areas are being processed; generally later removed; also short for photomask, typically a transparent negative used to print a pattern during lithography


MEMORY CELL CAPACITOR
the storage part of a DRAM cell; information is retained as a charge in the capacitor


MEMS
see micro-electromechanical system


METAL GATE
a type of transistor gate where the material used for the gate electrode is a metal, rather than traditional polysilicon


METAL HARDMASK (MHM)
a metal layer that may be used in critical patterning applications to improve etch selectivity and profile control


METALLIZATION
the process of depositing metal films, for example, the tungsten contacts and copper interconnects (wiring) in an integrated circuit


MHM
see metal hardmask


MICRO-ELECTROMECHANICAL SYSTEM (MEMS)
a miniature device generally consisting of a central component for data processing (such as a microprocessor) and other components that interact with their surroundings (such as micro-sensors)


MICRON (µm)
a unit of length equal to 1 x 10−6 meters; also known as micrometer


MICROPROCESSOR
a type of logic chip; also called a central processing unit (CPU)


MIDDLE-OF-LINE (MOL)
the set of wafer processing steps used to create the structures that provide the local electrical connections between transistors; mainly gate contact formation; occurs after front-end-of-line (transistors) and before back-end-of-line (wiring) processes


MILLIMETER (mm)
a unit of length equal to 1 x 10-3 meters; commonly used in the semiconductor industry to describe the diameter of a silicon wafer, for example, a 300 mm wafer


mm
see millimeter


MOL
see middle-of-line


MOORE'S LAW
an observation made by Gordon Moore in 1965 and later revised in 1975 that the number of transistors in an integrated circuit doubles roughly every two years, while the cost per IC decreases


MRAM
see magnetoresistive random-access memory


MSSD
see multi-station sequential deposition


MSSP
see multi-station sequential processing


MULTI-STATION SEQUENTIAL DEPOSITION (MSSD)
a tool architecture with multiple deposition stations designed to improve film uniformity; allows multiple wafers to be processed at the same time, thereby also improving productivity


MULTI-STATION SEQUENTIAL PROCESSING (MSSP)
a tool architecture with multiple stations designed to improve process repeatability; also allows processing multiple wafers at the same time, thereby also improving productivity


MULTIPLE PATTERNING
a manufacturing strategy used to create patterns that are more dense than would be possible with a single lithography step; involves decomposing a pattern into two or more separate, easier-to-print lithography steps or using a self-aligned patterning technique




N

NAND
short for NAND flash memory; a type of memory cell that connects transistors in a way that resembles the NAND (not-and) logic operator; often used in memory cards, USB drives, and solid state drives


NANOMETER (nm)
a unit of length equal to 1 x 10−9 meters; commonly used in the semiconductor industry to describe device dimensions as well as technology nodes, for example, the 10 nm node


nm
see nanometer


NON-UNIFORMITY
a measure of the inconsistency or variation of a process result on the wafer, for example, changes in film thickness; low non-uniformity is desirable


NUCLEATION LAYER
a thin layer of material generally used to aid subsequent metal film growth, for example, tungsten CVD for gapfill




O

OEM
see original equipment manufacturer


ORIGINAL EQUIPMENT MANUFACTURER (OEM)
a supplier that designs and manufactures equipment; in the semiconductor industry, distinguished from second-source suppliers who market components for equipment they do not design or manufacture


OXIDE
an insulating material; usually refers to silicon dioxide (SiO2)




P

PACKAGING
the process of enclosing a chip in a protective container (package) and providing power and signal connectivity


PARTICLE
a miniature piece of unwanted material on the wafer; depending on its size and location, may be a defect that impacts device performance or yield


PATTERNING
the processes involved in creating the features of an integrated circuit; includes design transfer using lithography and steps such as deposition and etch


PECVD
see plasma-enhanced vapor deposition


PHOTORESIST (PR)
a photosensitive material used to transfer a pattern onto a wafer during photolithography; defines the areas that will subsequently be processed


PHOTORESIST STRIP
a process that removes remaining photoresist from the wafer, typically following ion implant or etch processes; usually a dry process (using plasma) but may also be a wet process (using liquid chemicals)


PHYSICAL VAPOR DEPOSITION (PVD)
a process that deposits a thin, conductive film by using sputtering



PITCH
the distance from the center of one feature to the center of an adjacent feature, for example, from the center of one metal line to the center of an adjacent line


PLASMA
a state of matter made up of free electrons and ions; created by sending a charge through a gas


PLASMA ETCH
a process in which plasma is used to selectively remove material from the wafer through chemical and/or physical (ion bombardment) mechanisms


PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION (PECVD)
a process that uses a plasma to lower deposition temperatures relative to conventional chemical vapor deposition (CVD)


PMD
see pre-metal dielectric


PR
see photoresist


PRE-METAL DIELECTRIC (PMD)
an insulating material that provides electrical isolation between the transistors and the first interconnect layer


PROCESS FLOW
the order in which a set of semiconductor manufacturing processes is performed to fabricate devices on a wafer; there may be several hundred individual steps in a process flow



Q

QPT
quadruple patterning technology; see quadruple patterning


QUADRUPLE PATTERNING
a multiple patterning technique that increases feature density by a factor of four compared to using a single lithography step; involves either decomposing the mask into multiple easier-to-print lithography steps or using self-aligned quadruple patterning (SAQP)





R

RDL
see redistribution layer


REACTIVE ION ETCH (RIE)
a plasma etch process involving chemically reactive species (ions) that are accelerated toward the wafer in a low-pressure environment


REDISTRIBUTION LAYER (RDL)
an extra layer added to the chip during packaging to re-route electrical connection points


RESIDUE
unwanted material left on the wafer from previous processes; depending on the location and quantity, may be a defect that impacts device performance and/or yield


RIE
see reactive ion etch





S

SAC
see self-aligned contact


SADP
see self-aligned double patterning


SAQP
see self-aligned quadruple patterning


SEED LAYER
an ultra-thin film deposited to help initiate subsequent deposition; sometimes referred to as a nucleation layer


SELECTIVITY
a measure of the different removal rates between two materials; the faster one material is removed relative to another, the higher the selectivity


SELF-ALIGNED CONTACT (SAC)
a method of creating device contacts by using etch selectivities to follow the sidewall contour of the gate


SELF-ALIGNED DOUBLE PATTERNING (SADP)
a multiple patterning technique that increases feature density by 2X by depositing a spacer film on the sidewalls of a lithographically defined feature, followed by removing that original feature; the remaining spacers are then used to define the final pattern


SELF-ALIGNED QUADRUPLE PATTERNING (SAQP)
a multiple patterning technique that increases feature density by 4X by using repeated spacer films (similar to self-aligned double patterning) to define the desired pattern


SEMICONDUCTOR
a material with electrical conductivity between that of a conductor and an insulator; silicon is a commonly used semiconductor


SEMICONDUCTOR MANUFACTURING
the complete fabrication of semiconductor chips from front end (device and wiring) through back end (assembly, packaging, and test) processes


SEMICONDUCTOR MANUFACTURING EQUIPMENT
see wafer fabrication equipment


SHALLOW TRENCH ISOLATION (STI)
a structure that separates neighboring transistors or memory cells; a shallow trench is etched then filled with an insulating material


SINGLE-WAFER CLEAN
a process that removes particles and other materials one wafer at a time, in contrast to batch (multiple wafers); includes wet (using liquid chemistries) and dry (using plasma) processes


SIP
see system in package


SPACER
a deposited film commonly used to passivate sidewalls of the gate stack and to control the placement of dopants during ion implantation; also used to define the pattern in self-aligned multiple patterning schemes


SPIN CLEAN
a wet clean process in which the wafer is rotated at high velocity while being treated with chemical solutions; removes films, particles, and other contaminants that could affect device performance or yield


STI
see shallow trench isolation


SUBSTRATE
the starting material for the semiconductor manufacturing process, typically silicon; also referred to as a wafer


SYSTEM IN PACKAGE (SIP)
a packaging technology that combines integrated circuits of different functionalities into a single module that performs as a unified system




T

TECHNOLOGY NODE
commonly used to describe a device generation, for example, the 65 nm technology node is followed by the 45 nm technology node; historically referred to the smallest feature dimension


THERMAL BUDGET
the maximum thermal energy (determined by processing temperature and time) allowed for wafer fabrication processes to meet desired device performance and yield requirements


THIN FILM DEPOSITION
the process of forming sub-microscopic layers of conducting or insulating materials; includes dry processes (using plasma, such as PECVD) and wet (using liquid chemistries, such as ECD)


THROUGH-SILICON VIA (TSV)
a high aspect ratio structure that creates vertical electrical connections through a die or a wafer; enables higher functionality and smaller form factor


TRANSISTOR
a component that is used to amplify or switch electronic signals and electrical power; a primary component of an integrated circuit, which can contain up to several billion transistors


TRENCH
a long, narrow feature formed by anisotropic (directional) etching; can be shallow or deep


TSV
see through-silicon via





U

UBM
see underbump metallization


ULTRA LOW-K DIELECTRIC
an insulating material that has a dielectric constant (k value) generally less than 2.0-2.5; introducing porosity into the material is one way to obtain ultra low-k films


ULTRAVIOLET THERMAL PROCESSING (UVTP)
a technique that modifies the characteristics of a film through exposure to ultraviolet (UV) light and heat; used, for example, to improve the integrity of low-k films


UNDERBUMP METALLIZATION (UBM)
a metal deposition process that creates the electrical connection from the silicon die to a solder bump; used in packaging


UNIFORMITY
a measure of the consistency of process results (such as etch CD); may be measured within a die, across a wafer, from one wafer to another wafer, etc.; high uniformity is desirable


UVTP
see ultraviolet thermal processing




V

VARIABILITY
a measure of the difference in process results (such as film thickness); may be measured within a die, across a wafer, from one wafer to another wafer, etc.; low variability is desirable


VIA
an electrical pathway that connects two conductive layers


VOID
a gap or hole defect where material is missing in a structure (such as a hole in a via); may be a defect that impacts device performance or yield




W

WAFER
a round disk made of semiconducting material, often less than a millimeter thick; multiple chips are fabricated on each wafer; wafer sizes are defined by their diameter, for example, a 300 mm wafer


WAFER CLEANING
the process of removing particles, contaminants, and/or other unwanted materials from the wafer during manufacturing; includes wet (using liquid chemistries) and dry (using plasma) processes


WAFER FABRICATION EQUIPMENT (WFE)
the tools or machines used to manufacture integrated circuits


WAFER-LEVEL PACKAGING (WLP)
a strategy for packaging integrated circuits while they are still part of the wafer; in contrast to conventional packaging methods, which first slice the wafer into dies and then package each die individually


WAFER-TO-WAFER UNIFORMITY
a measure of the consistency in wafer processing results (such as etch profile) from one wafer to another; high uniformity is desirable


WET CLEAN
the process of removing particles, contaminants, and/or other unwanted materials using liquid chemistries


WFE
see wafer fabrication equipment


WITHIN-WAFER UNIFORMITY
a measure of the consistency in wafer processing results (such as film thickness) across a wafer; high uniformity is desirable


WLP
see wafer-level packaging


WORD LINE
the path used to select all the memory cells in a row; connects the gates of the cells in a row that makes up a two-dimensional array





Y

YIELD
the percentage or number of die that pass all testing and meet specified performance criteria (sometimes referred to as “good die”); high yield is desirable







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