Deep silicon etch is critical to the manufacture of devices used in a range of important applications from mobile products, automotive, and security to big data – servers, cloud computing, and graphics. For example, pixel isolation in CMOS image sensors (CIS) for smartphones and TSVs that connect stacked die and memory cells involve tall structures formed by these etch processes. With continued scaling, aspect ratios are increasing. In deep trench isolation, this is due to smaller critical dimensions (CDs) and deeper trenches, while for TSVs, shrinking CDs increase this ratio. One approach for creating these structures is to quickly switch between etch and deposition, thereby both carving the feature and layering material on the walls to protect them. Due to higher aspect ratios and multiple materials being etched, managing sidewall “scallop” size and roughness; top and bottom CD, etch depth, and cross-wafer uniformity; and profile tilt is now more challenging than ever. In addition, these larger features require high etch rates to maintain productivity for cost-efficient manufacturing.