- Exceptional uniformity, repeatability, and tunability enabled by a unique multi-frequency, small-volume, confined plasma design
- High productivity with low defectivity, enabled by in-situ multi-step etch and continuous plasma capability
- Low-risk, cost-effective upgrades that extend product life and maximize return on investment
- Ultra-high selectivity plasma-enhanced atomic layer etching (ALE) using Lam’s Advanced Mixed Mode Pulsing (AMMP™) technology
- Exelan® Flex®
- Exelan® Flex45™
- Flex® D Series
- Flex® E Series
- Flex® F Series
- Flex® G Series
- Flex® H Series
- Low-k and ultra low-k dual damascene
- Self-aligned contacts
- Capacitor cell
- Mask open
- 3D NAND high aspect ratio hole, trench, contact
Flex Product Family
Products
Atomic Layer Etch (ALE) Cryogenic Etching Reactive Ion Etch (RIE)
Dielectric etch carves patterns in insulating materials to create barriers between the electrically conductive parts of a semiconductor device. For advanced devices, these structures can be extremely tall and thin and involve complex, sensitive materials. Slight deviations from the target feature profile – even at the atomic level – can negatively affect electrical properties of the device.
To precisely create these challenging structures, Lam’s Flex® product family offers differentiated technologies and application-focused capabilities for critical dielectric etch applications. For some applications, select models are also available through our Reliant® Systems as refurbished products, providing lower cost of ownership with the same quality assurance and performance as new systems.
Industry Challenges
Dielectric etch faces multiple challenges due to new materials, complex new integration schemes, and scaling at advanced technology nodes. These new materials and integration schemes require the ability to etch multi-layer film stacks, often with extreme selectivity from one film to another. Chipmakers’ desire to reduce overall cost per wafer has placed an increased emphasis on the ability to etch multiple films in situ. Scaling challenges include creating optimal etched profiles at increasingly higher aspect ratios, in particular for memory cell capacitor structures and contacts, while providing repeatable dimension control in high-volume production. For logic devices, interconnect scaling drives high-selectivity etching of various low-k materials without increasing the k value of the dielectric film or adversely impacting device performance.