配線工程はチップ上の何10億個もの回路素子(トランジスタやコンデンサなど)を繋ぐために複雑な層間配線を形成する物です。チップ上の素子密度が高まるにつれ、全てを正しく繋ぐのに必要な配線層も増えるので、生産工程は難しくなります。現実問題として、微細化による寸法の縮小により、最先端のデバイスにおいては配線がチップの処理速度を遅くする要因になってきています。そのため、メタル接合の電気抵抗を低減する技術や、絶縁性能を高めるための新たな誘電体材料が必要になってきています。 最先端の高性能電子デバイスで採用される配線構造は極めて微細な構造で、しかも複雑な薄膜層を使います。そのため、柔軟性が高く、精密なプロセス能力が必要です。
ラムリサーチのソリューション
To keep pace with Moore's Law and enable greater interconnect scaling, the semiconductor ecosystem is continually experimenting with variations of materials. Tungsten has been the interconnect metal of choice for nearly a quarter century in NAND, DRAM, and logic/foundry middle-of-line applications. But scaling requirements are now pushing the boundaries of what is possible with tungsten. A variety of metals are being considered, but one — molybdenum — is an especially promising candidate. At the atomic dimensions required for advanced chipmaking, moly is emerging as the most suitable material to replace tungsten, creating a major inflection in the industry.
Cu’s resistivity depends on its crystal structure, void volume, grain boundaries and material interface mismatch, which becomes more significant at smaller scales. The formation of Cu wires is traditionally done by etching a trench pattern in low-k silicon dioxide using a trench etch process, and subsequently filling the trench with Cu via a damascene flow. Unfortunately, this method produces multi-crystalline structures with significant grain boundaries and voids, which increases the Cu wire resistance. A highly resistive TaN liner material is also utilized in this process to prevent Cu diffusion during the damascene annealing process.