The interconnect makes up the intricate wiring that connects the billions of individual components (transistors, capacitors, etc.) on a chip. As smaller and smaller devices are packed closer together, more interconnect levels are needed, and connecting everything becomes increasingly challenging. In fact, as the shrinking of feature dimensions has continued, interconnects are now becoming the speed bottleneck in today’s most advanced chips. As a result, techniques that minimize resistance of the metal connections and novel dielectric materials that boost insulating capacity are needed. To produce the latest high-performance electronic devices, advanced interconnect structures involve narrow geometries and complex film layers, which require increasingly flexible and precise process capabilities.
Our Solutions
Coronus systems focus on the bevel edge to enhance overall yield. Semiconductor processing can cause residues and roughness to accumulate along the wafer edge where they may flake off, drift to other areas, and create defects that cause a device to fail. Coronus etch products remove bevel residues and Coronus deposition protect the wafer bevel from damage.
Our Reliant deposition products enable roadmaps for Specialty Technologies and extend the productive life of fabs.
To keep pace with Moore's Law and enable greater interconnect scaling, the semiconductor ecosystem is continually experimenting with variations of materials. Tungsten has been the interconnect metal of choice for nearly a quarter century in NAND, DRAM, and logic/foundry middle-of-line applications. But scaling requirements are now pushing the boundaries of what is possible with tungsten. A variety of metals are being considered, but one — molybdenum — is an especially promising candidate. At the atomic dimensions required for advanced chipmaking, moly is emerging as the most suitable material to replace tungsten, creating a major inflection in the industry.
Cu’s resistivity depends on its crystal structure, void volume, grain boundaries and material interface mismatch, which becomes more significant at smaller scales. The formation of Cu wires is traditionally done by etching a trench pattern in low-k silicon dioxide using a trench etch process, and subsequently filling the trench with Cu via a damascene flow. Unfortunately, this method produces multi-crystalline structures with significant grain boundaries and voids, which increases the Cu wire resistance. A highly resistive TaN liner material is also utilized in this process to prevent Cu diffusion during the damascene annealing process.